For yield and performance repeatability the control of capacitor values is critical. It is desirable to have on-wafer capacitors have a capacitance value within a three percent (3%) tolerance. Too much variation in the capacitor values impacts the yield of any circuits, such as power amplifier circuits, or integrated passive networks, in which the capacitors are used. Two common places uses for precision capacitors are inter-stage matching and output matching. In particular, harmonic traps are becoming popular and require a greater degree of control for the capacitor value because it interacts with bond wire inductance.
What has been previously proposed to control the value of the capacitors is to wire in capacitors of the same type (just connecting capacitors made from the same dielectric at the same time) but this approach requires extra layout area. In addition, for “stacked” capacitors, this method cannot be employed because the capacitor cannot be measured before the process wiring is completed, and it would require an additional metal layer, thereby increasing cost.
For example, referring to FIGS. 1A and 1B, one prior art method is shown where the capacitor value is changed by modifying the size of the top plate of the capacitor. Referring to FIG. 1A, capacitor 10 having a capacitor value is formed by a bottom plate P1 12 and a top plate P2 14. The capacitor value can be changed by modifying the top plate size, as shown in FIG. 1B. The capacitor 10′ having a different capacitor value than capacitor 10 is formed by a bottom plate P1 12 and modified top plate P2′ 14′, where the modified top plate P2′ 14′ is of a different size than top plate P2 14 in FIG. 1A. However, this type of change is done as a mask revision, and is not done in response to measuring the capacitor value of a specific wafer, and thus only retargets the “nominal” capacitor. This change cannot be “adapted” because it is not possible to measure the value of the capacitor, and then correct the value of the capacitor, using this configuration.
FIG. 2 shows another prior art approach, where three side by side capacitors are shown, with a center capacitor formed by a bottom plate 21 and a top plate 22, and two adjacent capacitors—a left capacitor 24, which is formed by bottom plate 25 and top plate 26, and a right capacitor 28, which is formed by a bottom plate 29 and a top plate 30. In order to add to the capacitor value, the center capacitor 20 can then be wired to the left capacitor 24 by means of a wire 32 between top plate 26 of left capacitor 24 and the top plate 22 of center capacitor 20 and a wire 34 between bottom plate 25 of the left capacitor 24 and the bottom plate 21 of the center capacitor 20. In order to further add to the capacitor value, the center capacitor 20 can then be wired to the right capacitor 28 by means of a wire 36 between top plate 30 of right capacitor 28 and the top plate 22 of center capacitor 20 and a wire 38 between bottom plate 29 of the right capacitor 28 and the bottom plate 21 of the center capacitor 20.
This method requires an additional wiring layer be available above the level of the capacitor. This method would require a large amount of space (capacitors are side-by-side and design rules will make them some distance apart—bottom plates would also need to be connected separately). In a silicon process, this method would be implemented using a combination of vias and wiring.
The present disclosure describes in-line methods for making adaptive capacitors resulting in an on-wafer capacitor that can be corrected—in the wafer process. In addition, the proposed solution minimizes the layout area required for adaptation.